YUNOVA · Computer Organisation & Architecture
Module 10: Memory in depth
Cache performance and AMAT numericals
Key points
- AMAT = hit time + miss rate × miss penalty.
- For two cache levels, the L1 miss penalty is itself the AMAT of L2.
- Lowering miss rate or miss penalty both reduce average access time.
Virtual memory, paging and the TLB
Key points
- Paging splits virtual memory into pages mapped to physical frames by a page table.
- The TLB caches recent page-table entries so most translations skip memory.
- A page fault occurs when the page is not in main memory and must be loaded.
Memory interleaving and RAM/ROM organisation
Key points
- Interleaving spreads consecutive addresses across memory banks for parallel access.
- Low-order interleaving uses the lowest address bits to pick the bank.
- Larger memories are built from smaller RAM/ROM chips using decoders and chip selects.